HDI PCB Capability
HDI PCB Fabrication: Laser Microvia, Build-Up, and DFM Review
HDI PCB fabrication using laser microvias, blind and buried vias, and sequential build-up layers. APTPCB reviews stackup, via architecture, impedance, assembly interface, and required evidence before manufacturing release.
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What are the HDI PCB fabrication capabilities at APTPCB?
HDI PCB base material parameters
| Material Family | Typical Tg (°C) | Typical Dk @ 1 GHz | Typical Df @ 1 GHz | CTE Z-axis (ppm/°C) | Common Grades |
|---|---|---|---|---|---|
| Standard FR-4 | 130–140 | 4.2–4.6 | 0.015–0.025 | 2.8–3.5 | KB-6160, N4000-13 |
| Mid-Tg FR-4 | 150–160 | 4.1–4.4 | 0.013–0.020 | 2.6–3.2 | KB-6165, IS410 |
| High-Tg FR-4 | 170–180 | 3.9–4.2 | 0.010–0.018 | 2.4–3.0 | KB-6167F, FR408HR, IT-180A |
| Low-Loss FR-4 | ≥170 | 3.3–3.7 | 0.001–0.003 | 2.0–2.5 | Megtron 6/7, I-Speed |
| RF / PTFE | >260 (service) | 2.1–3.5 | 0.0002–0.004 | 1.5–2.5 | RO4350B, RT/duroid 5880 |
Values are typical ranges for planning. The binding material specification uses the grade and construction code from the datasheet. Confirm Dk/Df at the frequency and test method used for the impedance model.
HDI PCB trace, space and etch compensation by copper weight
| Finished Copper | Thickness | Min Trace / Space (HDI) | Min Annular Ring | CAM Etch Compensation (per side) |
|---|---|---|---|---|
| 0.5 oz (18 µm) | 18 µm | 4 / 4 mil (100 / 100 µm) | 4 mil | +1.5 mil |
| 1 oz (35 µm) | 35 µm | 5 / 5 mil (125 / 125 µm) | 5 mil | +2.0 mil |
| 2 oz (70 µm) | 70 µm | 6 / 6 mil (150 / 150 µm) | 7 mil | +3.0 mil |
| 3 oz (105 µm) | 105 µm | 8 / 8 mil (200 / 200 µm) | 10 mil | +4.0 mil |
HDI trace/space limits apply to the build-up layers. Outer-layer geometry for HDI boards follows the same minimums as standard rigid multilayer for the same copper weight.
HDI PCB laser microvia, blind/buried via, and drilling tolerances
| Parameter | Standard Limit | Tolerance / Condition | Engineering Verification |
|---|---|---|---|
| Laser microvia diameter | 0.075 mm (3 mil) | Board thickness 0.3–1.2 mm | Aspect ratio, capture pad, and fill reviewed per build-up layer |
| Laser microvia depth | 0.025–0.100 mm dielectric | Aspect ratio ≤ 0.75:1 | Dielectric thickness, copper condition, and laser energy reviewed |
| Stacked microvia | Requires fill + cap per layer | Defined build-up sequence | Fill material, cap plating, target land, and interface inspection confirmed together |
| Staggered microvia | Reduced stack dependency | By review | Stagger distance, target lands, and routing reviewed |
| Blind via (outer to inner) | Defined by approved stack-up drawing | Lamination stage mapping | Layer span, dielectric thickness, and registration reviewed |
| Buried via (inner to inner) | Defined by approved stack-up drawing | Sequential lamination stage | Registration, plating, and dielectric reviewed per lamination cycle |
| Via-in-pad (VIPPO) | Filled + capped by review | Pad planarity required | Fill system, cap requirement, surface finish, and stencil strategy confirmed |
| Mechanical drill (through-hole) | 0.15 mm (6 mil) min finished | Aspect ratio ≤ 10:1 | Drill deflection and plating reviewed at DFM |
| PTH positional tolerance | ±0.05 mm (±2 mil) standard | ±0.03 mm (±1.2 mil) advanced | Requires dedicated panel tooling |
Microvia diameter, capture pad, target land, and build-up sequence are project-specific. Do not combine minimum drill, minimum trace, and minimum spacing without a stack-up-specific DFM review.
HDI PCB board tolerances and surface finish options
| Parameter | Standard Capability | Advanced / Precision | Notes |
|---|---|---|---|
| Finished board thickness | 0.3–3.2 mm | ±0.05 mm on specific constructions | Thickness and tolerance must align with the build-up sequence |
| Impedance — single-ended | ±7% (standard) | ±5% (precision) | Requires coupon, TDR measurement, and agreed construction |
| Impedance — differential | ±7% (standard) | ±5% (precision) | Pair geometry, reference plane, and coupon location reviewed |
| Bow and twist | ≤ 0.5% for fine-pitch / BGA | ≤ 0.3% with tight tooling | Measured per IPC-TM-650 2.4.22; critical for sequential lamination |
| ENIG | Ni 3–6 µm; Au 0.05–0.15 µm | Ni 4–6 µm; Au 0.08–0.12 µm | Most common finish for fine-pitch BGA on HDI |
| Immersion silver | 0.05–0.20 µm | With anti-tarnish packaging | Shelf life limited; specify storage and packaging |
| OSP | Film 0.2–0.5 µm | Single thermal cycle only | Not recommended for multiple reflow without reprocessing |
HDI builds are sensitive to bow and twist because sequential lamination can accumulate stress. Specify flatness requirements when the board will receive fine-pitch BGA or CSP components.
HDI PCB DFM rules to check before layout release
| Design rule | Limit on this page | Why it matters |
|---|---|---|
| Laser microvia diameter and depth | 0.075 mm diameter; depth per build-up | Aspect ratio and capture pad must be compatible with the dielectric and copper condition |
| Stacked vs staggered microvia | Stacked requires fill + cap per layer; staggered reduces stack dependency | Stacked structures accumulate fill, cap, and alignment risk through each build-up layer |
| Via-in-pad | Filled + capped by review; pad planarity required | Without fill and cap, the barrel creates a solderability and coplanarity problem under BGA |
| Blind / buried via architecture | Defined by approved stack-up drawing | The lamination sequence, registration tooling, and dielectric type must match the approved build-up |
| Fine-pitch BGA and microvia architecture | HDI required when pitch ≤ 0.5 mm | Standard through-hole vias cannot fan out 0.4 mm or 0.5 mm pitch without yield loss |
| Impedance tolerance | ±7% standard; ±5% precision requires coupon + TDR | Trace geometry, dielectric constant, copper profile, and coupon measurement all affect achievable tolerance |
| Copper balance between paired layers | Within ±15% area | Unbalanced copper creates bow and twist that misaligns inner layers during sequential lamination |
| Trace / space vs copper weight on build-up layers | 4/4 mil @ 0.5 oz up to 6/6 mil @ 2 oz | Etch compensation grows with copper thickness; check the row for the finished weight |
HDI DFM review is more sensitive to parameter interactions than standard multilayer. A board at the minimum of several parameters simultaneously is higher-risk.
Standard multilayer vs HDI: choose by constraint, not by label
| Decision point | Standard multilayer is usually sufficient when | HDI review is justified when | Release question |
|---|---|---|---|
| Package escape | Plated through-holes and conventional fan-out route the package without violating approved design rules. | Fine-pitch BGA or dense module escape cannot be completed inside the available layers and outline. | Which pins, rows, or keepouts create the routing limit? |
| Board outline | The enclosure allows enough area for conventional vias, routing channels, test access, and assembly clearances. | The outline is fixed and routing density forces smaller interconnects or selective layer transitions. | Is the outline fixed, and what value does size reduction create? |
| Layer transitions | Signals can transition through the full stack without excessive stubs, congestion, or reference discontinuities. | Blind, buried, or microvia transitions are needed to free routing channels or control transition depth. | Which layers must connect, and which reference plane supports each transition? |
| Via-in-pad | Dog-bone fan-out or offset vias fit while preserving solderable pad geometry. | The package pitch or thermal path requires a via in a component pad. | Must the via be filled and capped, and what evidence is required? |
| Commercial case | Conventional fabrication meets size and performance targets with fewer special processes. | HDI reduces total product size, layer congestion, connector count, or system volume enough to justify added process steps. | What outcome offsets the extra lamination, fill, inspection, and qualification effort? |
Six engineering release gates before HDI production launch
| Release gate | What is reviewed | Release signal |
|---|---|---|
| 1. Architecture | Standard multilayer vs HDI, 1+N+1 vs 2+N+2, via map, stacked or staggered transitions, buried vias, and selective via-in-pad. | Every interconnect depth and lamination stage is defined in the stack-up and drill data. |
| 2. Material and stack-up | Material grade or property set, copper weight, dielectric construction, finished thickness, copper balance, and supply constraints. | An approved stack-up identifies materials, copper, dielectric spacing, thickness, and allowed substitutions. |
| 3. Geometry and drilling | Microvia diameter and depth, aspect ratio, lands, annular features, trace and space, and registration needs. | CAM rules match the released fabrication data and any exceptions have customer disposition. |
| 4. Plating, fill, and finish | Microvia fill, via plug and cap, copper build, pad planarity, surface finish, and solderable-feature requirements. | The drawing and purchase specification define the applicable process and acceptance criteria. |
| 5. Electrical and assembly interface | Impedance table, reference layers, coupons, netlist, BGA escape, stencil and reflow needs, warpage sensitivity, and test access. | Fabrication and assembly requirements do not contradict each other and the validation plan is agreed. |
| 6. Quality records and change control | Applicable IPC class or customer specification, inspection method, sampling, first article, lot traceability, reports, and deviation handling. | Required evidence, frequency, file revision, and approval ownership are stated on the order. |
What these HDI PCB specifications do not cover
HDI PCB fabrication FAQ
What makes a board an HDI board instead of a standard multilayer PCB?
An HDI board uses higher-density interconnect structures such as laser microvias, blind or buried vias, build-up layers, or selective via-in-pad to solve routing and package-escape constraints that a conventional plated-through-hole multilayer cannot solve cleanly. HDI should be selected for a defined routing, size, or electrical need rather than as a default technology label.
What is the difference between 1+N+1 and 2+N+2 HDI?
A 1+N+1 stack-up has one build-up layer on each side of the core, while 2+N+2 has two build-up layers on each side. The additional build-up layer increases routing access but also adds lamination, registration, plating, inspection, cost, and schedule dependencies.
Should HDI microvias be stacked or staggered?
Use staggered microvias when routing space permits because the structure can avoid some fill and stacking dependencies. Stacked microvias may be necessary for dense vertical transitions, but the fill, cap, alignment, plating, and inspection requirements must be released together.
Does every fine-pitch BGA require filled and capped via-in-pad?
No. Via-in-pad should be used where package pitch, fan-out, thermal, or routing constraints justify it. When a via sits in a solderable pad, define the fill and cap requirement, finished planarity, surface finish, stencil strategy, and X-ray or other assembly evidence before release.
What is the smallest laser microvia on an HDI board?
0.075 mm (3 mil) diameter with depth determined by the dielectric thickness in the build-up layer. The capture pad and target land are reviewed against the stack-up, material, and fill requirement.
What quality evidence should be specified for an HDI PCB?
Specify the evidence needed for the actual risks: netlist electrical test, AOI, microsection locations, microvia fill or cap review, registration evidence, impedance coupon and TDR report, dimensional report, material records, lot traceability, or assembly X-ray. State which records are required and whether they apply to first article, sampling, or each lot.
What bow and twist limits apply to HDI boards?
Target ≤0.5% for fine-pitch BGA or CSP assemblies; ≤0.3% with tight tooling control. Sequential lamination can accumulate stress, so flatness requirements should be stated when the board will receive dense surface-mount components.
What files are needed for an HDI PCB quote?
Send Gerber X2, ODB++, or IPC-2581 data; NC drill and netlist files; the proposed stack-up; via and drill table; fabrication drawing; impedance table; material and surface-finish requirements; board outline and tolerances; quantities and due date; and the BOM, placement data, and assembly drawing when PCBA is included.
Which HDI capability limits can be confirmed before DFM review?
APTPCB publishes a 4–32 layer rigid PCB range. Exact microvia diameter, aspect ratio, capture pad, trace and space, copper build, impedance tolerance, finished thickness, and sequential-lamination feasibility depend on the complete material, stack-up, geometry, panel, quantity, and evidence requirements and become binding only after DFM review.
How is an HDI PCB construction reviewed?
HDI fabrication uses microvias, sequential lamination and fine features to route dense interconnects. Submit the proposed build-up, via structure and reliability requirements so the feasible construction and acceptance evidence can be confirmed.
What drives HDI PCB cost and lead time
Request an HDI PCB fabrication and DFM review
Send your stack-up, via map, fabrication data, impedance requirements, quantities, due date, and required evidence. APTPCB will return a project-specific feasibility and quote response.