[{"data":1,"prerenderedAt":397},["ShallowReactive",2],{"blog-design-for-assembly-checklist-en":3,"header-nav-en":69},{"title":4,"description":5,"date":6,"category":7,"image":8,"readingTime":9,"wordCount":10,"timeRequired":11,"htmlContent":12,"tags":13,"slug":19,"jsonld":20},"Design for Assembly Checklist: What to Freeze Before PCBA Release","A practical engineering guide to design for assembly checklist review, covering package governance, orientation discipline, mixed-process planning, inspection visibility, test access, and release-readiness gates.","2026-05-13","technology","/assets/img/blogs/2025/12/design-for-assembly-checklist.png",12,2216,"PT12M","\u003Cul>\n\u003Cli>A design for assembly checklist should be treated as a \u003Cstrong>release-readiness review\u003C/strong>, not as a generic list of layout tips.\u003C/li>\n\u003Cli>The most useful boundary is to separate \u003Cstrong>package and footprint governance\u003C/strong>, \u003Cstrong>orientation discipline\u003C/strong>, \u003Cstrong>process-route fit\u003C/strong>, \u003Cstrong>inspection visibility\u003C/strong>, and \u003Cstrong>test access\u003C/strong>.\u003C/li>\n\u003Cli>A board can be electrically complete and still be difficult to release if the assembly route, hidden-joint exposure, or documentation package remain unstable.\u003C/li>\n\u003Cli>A design for assembly checklist should explain what should be checked before first build and what should be frozen before the board enters a repeatable PCBA flow.\u003C/li>\n\u003C/ul>\n\u003Cblockquote>\n\u003Cp>\u003Cstrong>Quick Answer\u003C/strong>\nA design for assembly checklist is strongest when it reviews the board in order: package and footprint control, component-orientation discipline, mixed-process fit, inspection visibility, electrical-test access, and release-package alignment. Ask what still has to be cleaned up before the board can move into assembly, inspection, and first-build release without guesswork.\u003C/p>\n\u003C/blockquote>\n\u003Cp>For the broader view of how assembly inputs connect to inspection, electrical verification, and shipment gates, start with the \u003Ca href=\"/en/blog/pcba-assembly-test-quality-guide\">PCBA Assembly Test and Quality Guide\u003C/a>.\u003C/p>\n\u003Ch2 id=\"table-of-contents\" data-anchor-en=\"table-of-contents\">Table of Contents\u003C/h2>\n\u003Cul>\n\u003Cli>\u003Ca href=\"#first-review\">What should engineers review first?\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"#what-this-means\">What counts as DFA here?\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"#risk-areas\">Which checklist areas expose release risk fastest?\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"#inspection-and-test\">How do inspection and test planning connect to DFA?\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"#freeze-before-release\">What should be frozen before RFQ, first build, or release?\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"#next-steps\">Next steps with APTPCB\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"#faq\">FAQ\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"#references\">Public references\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"#author\">Author and review information\u003C/a>\u003C/li>\n\u003C/ul>\n\u003Ca id=\"first-review\">\u003C/a>\n\u003Ch2 id=\"what-should-engineers-review-first\" data-anchor-en=\"what-should-engineers-review-first\">What should engineers review first?\u003C/h2>\n\u003Cp>Start with \u003Cstrong>footprint governance, orientation consistency, process-route fit, inspection visibility, and test-access readiness\u003C/strong>.\u003C/p>\n\u003Cp>That order matters because DFA problems usually become expensive when they are discovered too late. If the board enters NPI with unstable package choices, unclear orientation logic, or unresolved access conflicts, the later inspection and test layers inherit work that should have been closed upstream.\u003C/p>\n\u003Cp>The first engineering questions are usually:\u003C/p>\n\u003Col>\n\u003Cli>Do the package and footprint choices still match the intended component families cleanly?\u003C/li>\n\u003Cli>Are polarity and pin-1-sensitive parts documented and placed with enough consistency to support setup and review?\u003C/li>\n\u003Cli>Does the assembly route still fit the population mix, especially if SMT, THT, selective solder, or hidden-joint inspection all matter?\u003C/li>\n\u003Cli>Can AOI, X-ray, ICT, flying probe, or FCT be planned without fighting avoidable access or visibility conflicts?\u003C/li>\n\u003Cli>Is the release package aligned well enough that BOM, assembly drawing, and quality plan describe the same board state?\u003C/li>\n\u003C/ol>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Review boundary\u003C/th>\n\u003Cth>What it answers\u003C/th>\n\u003Cth>What it does not prove\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>Footprint governance\u003C/td>\n\u003Ctd>Whether the package library and intended parts still align cleanly\u003C/td>\n\u003Ctd>That exact geometry is universally valid for every substitute\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Orientation consistency\u003C/td>\n\u003Ctd>Whether sensitive parts can be interpreted and reviewed without ambiguity\u003C/td>\n\u003Ctd>That the whole build package is already released\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Process-route fit\u003C/td>\n\u003Ctd>Whether the population still matches the planned assembly flow\u003C/td>\n\u003Ctd>That every inspection or test gate is already closed\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Inspection visibility\u003C/td>\n\u003Ctd>Whether visible and hidden-joint review can be planned sensibly\u003C/td>\n\u003Ctd>That powered behavior has been validated\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Test access\u003C/td>\n\u003Ctd>Whether electrical verification can be planned with the current design posture\u003C/td>\n\u003Ctd>That the product is ready to ship\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Ca id=\"what-this-means\">\u003C/a>\n\u003Ch2 id=\"what-counts-as-dfa-here\" data-anchor-en=\"what-counts-as-dfa-here\">What counts as DFA here?\u003C/h2>\n\u003Cp>Here, \u003Ccode>design for assembly checklist\u003C/code> means the \u003Cstrong>board-level readiness review that sits between layout completion and controlled PCBA release\u003C/strong>.\u003C/p>\n\u003Cp>That includes:\u003C/p>\n\u003Cul>\n\u003Cli>package-library and footprint review\u003C/li>\n\u003Cli>orientation and polarity discipline\u003C/li>\n\u003Cli>mixed SMT and THT route awareness\u003C/li>\n\u003Cli>hidden-joint and inspection-visibility awareness\u003C/li>\n\u003Cli>test-access review for later electrical or functional validation\u003C/li>\n\u003Cli>release-package alignment across BOM, drawing, and quality path\u003C/li>\n\u003C/ul>\n\u003Cp>It does not mean:\u003C/p>\n\u003Cul>\n\u003Cli>one universal list of spacing numbers for every board\u003C/li>\n\u003Cli>guaranteed yield or lead-time outcomes\u003C/li>\n\u003Cli>a claim that visual inspection alone is enough\u003C/li>\n\u003Cli>proof that system-level validation is finished\u003C/li>\n\u003C/ul>\n\u003Cp>That boundary matters because many DFA articles drift into invented geometry tables or generic manufacturing slogans. The better explanation is more disciplined:\u003C/p>\n\u003Cp>\u003Cstrong>DFA is the point where the team checks whether the board, the package, and the planned assembly flow still fit each other before release.\u003C/strong>\u003C/p>\n\u003Ca id=\"risk-areas\">\u003C/a>\n\u003Ch2 id=\"which-checklist-areas-expose-release-risk-fastest\" data-anchor-en=\"which-checklist-areas-expose-release-risk-fastest\">Which checklist areas expose release risk fastest?\u003C/h2>\n\u003Cp>The release risk usually shows up first in the places where design intent and assembly reality diverge.\u003C/p>\n\u003Ch3 id=\"1-package-library-and-footprint-governance\" data-anchor-en=\"1-package-library-and-footprint-governance\">1. Package-library and footprint governance\u003C/h3>\n\u003Cp>The checklist should confirm that the board is still using package definitions that match the intended component set cleanly.\u003C/p>\n\u003Cp>That means reviewing:\u003C/p>\n\u003Cul>\n\u003Cli>package-family identity\u003C/li>\n\u003Cli>footprint ownership and revision discipline\u003C/li>\n\u003Cli>polarity or pin-1 visibility\u003C/li>\n\u003Cli>whether late alternates still fit the same assembly assumptions\u003C/li>\n\u003C/ul>\n\u003Cp>If the package library is unstable, the rest of the DFA review becomes harder to trust.\u003C/p>\n\u003Ch3 id=\"2-orientation-discipline\" data-anchor-en=\"2-orientation-discipline\">2. Orientation discipline\u003C/h3>\n\u003Cp>Orientation-sensitive parts should not rely on tribal knowledge.\u003C/p>\n\u003Cp>The checklist should ask whether:\u003C/p>\n\u003Cul>\n\u003Cli>pin-1-sensitive parts remain obvious in the release package\u003C/li>\n\u003Cli>polarized components are easy to verify during setup and review\u003C/li>\n\u003Cli>the assembly drawing and placement package describe orientation consistently\u003C/li>\n\u003C/ul>\n\u003Cp>One of the worst NPI failures starts in the CAD library before a single component is mounted. Engineers define a symmetric QFN or LGA footprint without following a proper \u003Ccode>Zero-Orientation\u003C/code> rule such as \u003Ccode>IPC-7351\u003C/code> or \u003Ccode>IEC 61188-7\u003C/code>, then hand the centroid file to the SMT line as if the rotation convention were self-evident. It is not. The CAD zero angle can be off by 90 degrees or 180 degrees from the default \u003Ccode>EIA-481\u003C/code> tape-and-reel orientation. The situation becomes lethal when the designer also hides the Pin 1 mark under the package body to save space, leaving no reliable top-side cue for setup or optical review. The pick-and-place machine then installs the device in the wrong rotation without hesitation. AOI sees a top surface that still looks perfectly symmetric and returns a \u003Ccode>False Pass\u003C/code>. The first power-on event is where the mistake becomes visible. \u003Ccode>VCC\u003C/code> and \u003Ccode>GND\u003C/code> are now effectively crossed into a \u003Ccode>Dead short\u003C/code>, internal current spikes instantly, and the silicon fails hard enough to start \u003Ccode>Vaporized\u003C/code> wire bonds and visible smoke on the board. That is not a documentation error. It is a destroyed first article caused by weak orientation governance.\u003C/p>\n\u003Cp>For the orientation layer, see \u003Ca href=\"/en/blog/smt-component-polarity\">SMT Component Polarity\u003C/a>.\u003C/p>\n\u003Ch3 id=\"3-mixed-process-fit\" data-anchor-en=\"3-mixed-process-fit\">3. Mixed-process fit\u003C/h3>\n\u003Cp>Boards that combine dense SMT with connectors, terminals, or other through-hole hardware need a cleaner route review than a pure SMT board.\u003C/p>\n\u003Cp>The checklist should ask:\u003C/p>\n\u003Cul>\n\u003Cli>does the board still fit the planned SMT and THT flow?\u003C/li>\n\u003Cli>are selective or manual exceptions visible enough?\u003C/li>\n\u003Cli>does mixed-process handling change what should be frozen before first build?\u003C/li>\n\u003C/ul>\n\u003Cp>For that route split, see \u003Ca href=\"/en/blog/mixed-assembly-planning\">Mixed Assembly Planning\u003C/a>.\u003C/p>\n\u003Ch3 id=\"4-inspection-visibility\" data-anchor-en=\"4-inspection-visibility\">4. Inspection visibility\u003C/h3>\n\u003Cp>Inspection planning belongs inside DFA because some assembly risks are visible and some are not.\u003C/p>\n\u003Cp>That boundary matters when:\u003C/p>\n\u003Cul>\n\u003Cli>optical inspection is expected to catch visible orientation or placement issues\u003C/li>\n\u003Cli>hidden-joint packages push risk into X-ray review\u003C/li>\n\u003Cli>tall or dense neighborhoods reduce what the optical layer can confirm\u003C/li>\n\u003C/ul>\n\u003Ch3 id=\"5-test-access-readiness\" data-anchor-en=\"5-test-access-readiness\">5. Test-access readiness\u003C/h3>\n\u003Cp>Electrical-test planning should not be left until after the board is released if the design already creates access constraints.\u003C/p>\n\u003Cp>The checklist should ask whether the design posture still supports:\u003C/p>\n\u003Cul>\n\u003Cli>fixture-based ICT if the program later needs it\u003C/li>\n\u003Cli>fixture-free flying probe if the board is still changing\u003C/li>\n\u003Cli>functional-test access and programming expectations where applicable\u003C/li>\n\u003C/ul>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Checklist area\u003C/th>\n\u003Cth>Why it matters\u003C/th>\n\u003Cth>What goes wrong when it is ignored\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>Footprint governance\u003C/td>\n\u003Ctd>Keeps the physical implementation tied to the intended package family\u003C/td>\n\u003Ctd>Late uncertainty about what the board is actually designed to mount\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Orientation discipline\u003C/td>\n\u003Ctd>Prevents ambiguity during setup, FAI, and troubleshooting\u003C/td>\n\u003Ctd>Reversed or disputed placement intent\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Mixed-process fit\u003C/td>\n\u003Ctd>Keeps assembly-route assumptions realistic\u003C/td>\n\u003Ctd>Unexpected manual exceptions or process queries during NPI\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Inspection visibility\u003C/td>\n\u003Ctd>Separates visible-risk review from hidden-joint review\u003C/td>\n\u003Ctd>Overstated confidence in what AOI can actually prove\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Test access\u003C/td>\n\u003Ctd>Prevents late DFT conflict between layout and verification needs\u003C/td>\n\u003Ctd>Electrical-test planning becomes reactive instead of designed\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>A typical DFA failure chain starts when the package looks routable in CAD but the assembly window is already too narrow in production terms. A footprint or placement choice leaves weak polarity visibility, poor optical access, or too little separation between dense SMT and later hand or selective operations. The board still reaches the line because the mismatch looks manageable on screen. Reflow, selective solder, or rework then has to operate inside that narrowed window, visible defects are harder to screen, and electrical-test access is forced into a workaround posture. The result is not one abstract DFA concern. It is bridging, rework churn, blocked inspection confidence, or release delay caused by a package-to-process mismatch that should have been frozen earlier.\u003C/p>\n\u003Ca id=\"inspection-and-test\">\u003C/a>\n\u003Ch2 id=\"how-do-inspection-and-test-planning-connect-to-dfa\" data-anchor-en=\"how-do-inspection-and-test-planning-connect-to-dfa\">How do inspection and test planning connect to DFA?\u003C/h2>\n\u003Cp>DFA is upstream of inspection and test, but it should anticipate their needs.\u003C/p>\n\u003Cp>That means keeping the boundaries clear:\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Downstream layer\u003C/th>\n\u003Cth>What it mainly answers\u003C/th>\n\u003Cth>What DFA should do upstream\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>AOI\u003C/td>\n\u003Ctd>Whether visible placement and solder-related features can be screened optically\u003C/td>\n\u003Ctd>Preserve readable orientation and visible review intent\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>X-ray\u003C/td>\n\u003Ctd>Whether hidden joints or concealed structures need inspection evidence\u003C/td>\n\u003Ctd>Flag when hidden-joint risk changes the release posture\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>ICT or flying probe\u003C/td>\n\u003Ctd>Whether electrical defects can be screened with the chosen access model\u003C/td>\n\u003Ctd>Avoid preventable access conflicts\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>FCT\u003C/td>\n\u003Ctd>Whether the assembled board behaves correctly in powered context\u003C/td>\n\u003Ctd>Keep programming, connectors, and setup intent from becoming ambiguous\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>The safer rule is:\u003C/p>\n\u003Cp>\u003Cstrong>DFA should reduce avoidable downstream ambiguity, not pretend that downstream verification is unnecessary.\u003C/strong>\u003C/p>\n\u003Cp>Useful companion pages:\u003C/p>\n\u003Cul>\n\u003Cli>\u003Ca href=\"/en/blog/aoi-inspection-pcba\">AOI Inspection for PCBA\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/blog/xray-inspection\">X-Ray Inspection\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/blog/ict-vs-flying-probe\">ICT vs Flying Probe\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/pcba/testing-quality\">Testing & Quality\u003C/a>\u003C/li>\n\u003C/ul>\n\u003Ca id=\"freeze-before-release\">\u003C/a>\n\u003Ch2 id=\"what-should-be-frozen-before-rfq-first-build-or-release\" data-anchor-en=\"what-should-be-frozen-before-rfq-first-build-or-release\">What should be frozen before RFQ, first build, or release?\u003C/h2>\n\u003Cp>Before serious RFQ, first build, or release, freeze:\u003C/p>\n\u003Col>\n\u003Cli>the package-library and footprint choices that define the assembly posture\u003C/li>\n\u003Cli>orientation and polarity interpretation for sensitive parts\u003C/li>\n\u003Cli>the assembly route assumptions for SMT, THT, selective, or other special branches\u003C/li>\n\u003Cli>the inspection and test boundary, especially where visible review, hidden-joint review, and electrical verification differ\u003C/li>\n\u003Cli>the alignment between BOM, assembly drawing, placement data, and quality-plan expectations\u003C/li>\n\u003C/ol>\n\u003Cp>If those items are still moving, the design may still be functionally promising, but the assembly release package is not yet fully stable.\u003C/p>\n\u003Ca id=\"next-steps\">\u003C/a>\n\u003Ch2 id=\"next-steps-with-aptpcb\" data-anchor-en=\"next-steps-with-aptpcb\">Next steps with APTPCB\u003C/h2>\n\u003Cp>If you are preparing a dense PCBA first build and you are not fully certain that your CAD rotation model matches the machine's orientation logic, that mixed-height neighborhoods will survive wave-solder shadowing, or that hidden-pin packages still leave AOI enough visibility to catch the real defect, do not wait for first power-on to discover the answer. That is the point where many boards still look release-ready on screen while the assembly package is already carrying a preventable burn-up risk.\u003C/p>\n\u003Cp>Send the \u003Ccode>ODB++\u003C/code> or \u003Ccode>IPC-2581\u003C/code> release package, full \u003Ccode>BOM\u003C/code>, and \u003Ccode>XY\u003C/code> centroid data to \u003Ccode>sales@aptpcb.com\u003C/code> or through the \u003Ca href=\"/en/quote\">quote page\u003C/a>.\u003C/p>\n\u003Cp>APTPCB's NPI and DFA engineering team will return a \u003Cstrong>DFA Physical & Orientation Review\u003C/strong> within \u003Cstrong>24 hours\u003C/strong>. We will identify CAD zero-angle conflicts, verify machine-mount compatibility for complex package families, and flag assembly conditions that can turn an orientation mistake into an expensive first-build failure before you energize a single vulnerable device.\u003C/p>\n\u003Cp>If you need to go deeper before release, review:\u003C/p>\n\u003Cul>\n\u003Cli>\u003Ca href=\"/en/blog/pcba-assembly-test-quality-guide\">PCBA Assembly Test and Quality Guide\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/blog/assembly-bom-best-practices\">Assembly BOM Best Practices\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/blog/assembly-drawing-essentials\">Assembly Drawing Essentials\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/blog/mixed-assembly-planning\">Mixed Assembly Planning\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/blog/ict-vs-flying-probe\">ICT vs Flying Probe\u003C/a>\u003C/li>\n\u003C/ul>\n\u003Cdiv data-component=\"BlogQuickQuoteInline\">\u003C/div>\n\n\u003Ca id=\"faq\">\u003C/a>\n\u003Ch2 id=\"faq\" data-anchor-en=\"faq\">FAQ\u003C/h2>\n\u003C!-- faq:start -->\n\n\u003Ch3 id=\"is-a-dfa-checklist-only-about-component-spacing\" data-anchor-en=\"is-a-dfa-checklist-only-about-component-spacing\">Is a DFA checklist only about component spacing?\u003C/h3>\n\u003Cp>No. It is a broader release-readiness review covering package control, orientation discipline, process-route fit, inspection visibility, and test-access planning.\u003C/p>\n\u003Ch3 id=\"why-does-dfa-need-to-care-about-inspection\" data-anchor-en=\"why-does-dfa-need-to-care-about-inspection\">Why does DFA need to care about inspection?\u003C/h3>\n\u003Cp>Because the design determines what later inspection layers can and cannot see easily. That affects how confidently visible and hidden-joint risks can be separated.\u003C/p>\n\u003Ch3 id=\"does-dfa-replace-dft-or-test-planning\" data-anchor-en=\"does-dfa-replace-dft-or-test-planning\">Does DFA replace DFT or test planning?\u003C/h3>\n\u003Cp>No. DFA should anticipate those needs and avoid preventable conflicts, but electrical and functional verification still have their own downstream ownership.\u003C/p>\n\u003Ch3 id=\"what-makes-a-board-fail-dfa-review-most-often\" data-anchor-en=\"what-makes-a-board-fail-dfa-review-most-often\">What makes a board fail DFA review most often?\u003C/h3>\n\u003Cp>Usually not one dramatic defect, but a package that is still unstable: footprint questions, mixed-process ambiguity, weak orientation visibility, or unresolved release-package drift.\u003C/p>\n\u003Ch3 id=\"when-should-dfa-be-treated-as-complete\" data-anchor-en=\"when-should-dfa-be-treated-as-complete\">When should DFA be treated as complete?\u003C/h3>\n\u003Cp>Only when the package, assembly route, and verification boundaries are stable enough that first build does not depend on guesswork.\u003C/p>\n\u003C!-- faq:end -->\n\n\u003Ca id=\"references\">\u003C/a>\n\u003Ch2 id=\"public-references\" data-anchor-en=\"public-references\">Public references\u003C/h2>\n\u003Col>\n\u003Cli>\u003Cp>[KiCad Library Convention] (\u003Ca href=\"https://klc.kicad.org/\">https://klc.kicad.org/\u003C/a>)\nPublic CAD-library reference for controlled footprint-library construction and review discipline.\u003C/p>\n\u003C/li>\n\u003Cli>\u003Cp>\u003Ca href=\"https://webstore.iec.ch/en/publication/27498\">IEC 61188-7\u003C/a>\nPublic standards metadata for zero-orientation and CAD-library construction language.\u003C/p>\n\u003C/li>\n\u003Cli>\u003Cp>\u003Ca href=\"https://www.ipc.org/TOC/IPC-A-610H-toc.pdf\">IPC-A-610H Table of Contents\u003C/a>\nPublic standards anchor for workmanship and visible-assembly acceptability context.\u003C/p>\n\u003C/li>\n\u003Cli>\u003Cp>\u003Ca href=\"https://www.ipc.org/TOC/IPC-J-STD-001J_TOC.pdf\">IPC J-STD-001J Table of Contents\u003C/a>\nPublic standards anchor for soldered electrical and electronic assembly requirements context.\u003C/p>\n\u003C/li>\n\u003Cli>\u003Cp>\u003Ca href=\"/en/blog/pcba-assembly-test-quality-guide\">PCBA Assembly Test and Quality Guide\u003C/a>\nCompanion page for the layered release-readiness model that connects inputs, inspection, electrical verification, and release gates.\u003C/p>\n\u003C/li>\n\u003C/ol>\n\u003Ca id=\"author\">\u003C/a>\n\u003Ch2 id=\"author-and-review-information\" data-anchor-en=\"author-and-review-information\">Author and review information\u003C/h2>\n\u003Cul>\n\u003Cli>Author: APTPCB PCBA manufacturability and release-readiness content team\u003C/li>\n\u003Cli>Technical review: DFA, package-library, and NPI planning team\u003C/li>\n\u003Cli>Last updated: 2026-05-13\u003C/li>\n\u003C/ul>\n\n\u003Csection class=\"related-links\" aria-label=\"Related\">\u003Ch3>Related links\u003C/h3>\u003Cul>\u003Cli>\u003Ca href=\"/en/blog/pcba-assembly-test-quality-guide\">PCBA Assembly Test and Quality Guide\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/smt-component-polarity\">SMT Component Polarity\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/mixed-assembly-planning\">Mixed Assembly Planning\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/aoi-inspection-pcba\">AOI Inspection for PCBA\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/xray-inspection\">X-Ray Inspection\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/ict-vs-flying-probe\">ICT vs Flying Probe\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/pcba/testing-quality\">Testing & Quality\u003C/a>\u003C/li>\u003C/ul>\u003C/section>",[14,15,16,17,18],"design for assembly checklist","design for assembly","dfa checklist","pcba release readiness","assembly review","design-for-assembly-checklist",{"blog":21,"breadcrumb":30,"faq":44},{"@context":22,"@type":23,"headline":4,"description":5,"image":8,"url":24,"datePublished":6,"dateModified":6,"timeRequired":11,"keywords":25,"articleSection":7,"author":26,"publisher":29},"https://schema.org","BlogPosting","https://aptpcb.com/en/blog/design-for-assembly-checklist","design for assembly checklist, design for assembly, dfa checklist, pcba release readiness, assembly review",{"@type":27,"name":28},"Organization","APTPCB",{"@type":27,"name":28},{"@context":22,"@type":31,"itemListElement":32},"BreadcrumbList",[33,38,42],{"@type":34,"position":35,"name":36,"item":37},"ListItem",1,"Home","https://aptpcb.com/",{"@type":34,"position":39,"name":40,"item":41},2,"Blog","https://aptpcb.com/en/blog",{"@type":34,"position":43,"name":19,"item":24},3,{"@context":22,"@type":45,"mainEntity":46},"FAQPage",[47,53,57,61,65],{"@type":48,"name":49,"acceptedAnswer":50},"Question","Is a DFA checklist only about component spacing?",{"@type":51,"text":52},"Answer","No. It is a broader release-readiness review covering package control, orientation discipline, process-route fit, inspection visibility, and test-access planning.",{"@type":48,"name":54,"acceptedAnswer":55},"Why does DFA need to care about inspection?",{"@type":51,"text":56},"Because the design determines what later inspection layers can and cannot see easily. That affects how confidently visible and hidden-joint risks can be separated.",{"@type":48,"name":58,"acceptedAnswer":59},"Does DFA replace DFT or test planning?",{"@type":51,"text":60},"No. DFA should anticipate those needs and avoid preventable conflicts, but electrical and functional verification still have their own downstream ownership.",{"@type":48,"name":62,"acceptedAnswer":63},"What makes a board fail DFA review most often?",{"@type":51,"text":64},"Usually not one dramatic defect, but a package that is still unstable: footprint questions, mixed-process ambiguity, weak orientation visibility, or unresolved release-package drift.",{"@type":48,"name":66,"acceptedAnswer":67},"When should DFA be treated as complete?",{"@type":51,"text":68},"Only when the package, assembly route, and verification boundaries are stable enough that first build does not depend on guesswork.",{"pcbManufacturingColumns":70,"capabilityColumns":195,"resourceColumns":226,"pcbaColumns":266},[71,119,148,177],{"heading":72,"links":73},"PCB Product Families",[74,77,80,83,86,89,92,95,98,101,104,107,110,113,116],{"label":75,"path":76},"FR-4 PCB","/pcb/fr4-pcb",{"label":78,"path":79},"High-Speed PCB","/pcb/high-speed-pcb",{"label":81,"path":82},"Multilayer PCB","/pcb/multilayer-pcb",{"label":84,"path":85},"HDI PCB","/pcb/hdi-pcb",{"label":87,"path":88},"Flexible PCB","/pcb/flex-pcb",{"label":90,"path":91},"Rigid Flex PCB","/pcb/rigid-flex-pcb",{"label":93,"path":94},"Ceramic PCB","/pcb/ceramic-pcb",{"label":96,"path":97},"Heavy Copper PCB","/pcb/heavy-copper-pcb",{"label":99,"path":100},"High Thermal PCB","/pcb/high-thermal-pcb",{"label":102,"path":103},"Antenna PCB","/pcb/antenna-pcb",{"label":105,"path":106},"High Frequency PCB","/pcb/high-frequency-pcb",{"label":108,"path":109},"Microwave PCB","/pcb/microwave-pcb",{"label":111,"path":112},"Metal Core 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(PCB)","/pcb/npi-small-batch-pcb-manufacturing",{"label":160,"path":161},"High-Volume Production","/pcb/mass-production-pcb-manufacturing",{"label":163,"path":164},"High Layer Count PCB","/pcb/high-layer-count-pcb",{"label":166,"path":167},"PCB Fabrication Process","/pcb/pcb-fabrication-process",{"label":169,"path":170},"Advanced PCB Manufacturing","/pcb/advanced-pcb-manufacturing",{"label":172,"path":173},"Special PCB Manufacturing","/pcb/special-pcb-manufacturing",{"label":175,"path":176},"Multi-Layer Laminated Structure","/pcb/multi-layer-laminated-structure",{"heading":178,"links":179},"Specialties & Resources",[180,183,186,189,192],{"label":181,"path":182},"PCB Surface Finishes (ENIG / ENEPIG / HASL / OSP / Immersion)","/pcb/pcb-surface-finishes",{"label":184,"path":185},"Drilling & Vias (Blind / Buried / Via-in-Pad / Backdrill / Half Hole)","/pcb/pcb-drilling",{"label":187,"path":188},"PCB Stackup (Standard / High-Layer / Flex / Rigid-Flex / Aluminum)","/pcb/pcb-stack-up",{"label":190,"path":191},"Profiles (Milling / V-Scoring / Depaneling)","/pcb/pcb-profiling",{"label":193,"path":194},"Quality & Inspection (AOI + X-Ray / Flying Probe / PCB DFM Check)","/pcb/pcb-quality",[196,201,206,211,216,221],{"links":197},[198],{"label":199,"path":200},"Rigid PCB Capability","/capabilities/rigid-pcb",{"links":202},[203],{"label":204,"path":205},"Rigid-Flex Capability","/capabilities/rigid-flex-pcb",{"links":207},[208],{"label":209,"path":210},"Flex PCB Capability","/capabilities/flex-pcb",{"links":212},[213],{"label":214,"path":215},"HDI PCB Capability","/capabilities/hdi-pcb",{"links":217},[218],{"label":219,"path":220},"Metal PCB Capability","/capabilities/metal-pcb",{"links":222},[223],{"label":224,"path":225},"Ceramic PCB Capability","/capabilities/ceramic-pcb",[227,237,258],{"heading":228,"links":229},"Downloads",[230,233,236],{"label":231,"path":232},"Materials Datasheet / Processing Notes","/resources/downloads-materials",{"label":234,"path":235},"PCB DFM Guidelines","/resources/dfm-guidelines",{"label":175,"path":176},{"heading":238,"links":239},"Tools",[240,243,246,249,252,255],{"label":241,"path":242},"Gerber Viewer","/tools/gerber-viewer",{"label":244,"path":245},"PCB Viewer","/tools/pcb-viewer",{"label":247,"path":248},"BOM Viewer","/tools/bom-viewer",{"label":250,"path":251},"3D Viewer","/tools/3d-viewer",{"label":253,"path":254},"Circuit Simulator","/tools/circuit-simulator",{"label":256,"path":257},"Impedance Calculator","/tools/impedance-calculator",{"heading":259,"links":260},"FAQ & Blog",[261,264],{"label":262,"path":263},"FAQ","/resources/faq",{"label":40,"path":265},"/blog",[267,297,327,360],{"heading":268,"links":269},"Core Services",[270,273,276,279,282,285,288,291,294],{"label":271,"path":272},"Turnkey PCB Assembly","/pcba/turnkey-assembly",{"label":274,"path":275},"NPI & Small Batch PCB Assembly","/pcba/npi-assembly",{"label":277,"path":278},"Mass Production PCB Assembly","/pcba/mass-production",{"label":280,"path":281},"Flex & Rigid-Flex PCB Assembly","/pcba/flex-rigid-flex",{"label":283,"path":284},"SMT & Through-Hole Assembly","/pcba/smt-tht",{"label":286,"path":287},"BGA PCB Assembly","/pcba/bga-qfn-fine-pitch",{"label":289,"path":290},"Components & BOM Management","/pcba/components-bom",{"label":292,"path":293},"Box Build Assembly","/pcba/box-build-assembly",{"label":295,"path":296},"PCB Assembly Testing & Quality","/pcba/testing-quality",{"heading":298,"links":299},"Supporting Services",[300,303,306,309,312,315,318,321,324],{"label":301,"path":302},"Every Support Touchpoint","/pcba/support-services",{"label":304,"path":305},"Stencil Lab","/pcba/pcb-stencil",{"label":307,"path":308},"Components Sourcing","/pcba/component-sourcing",{"label":310,"path":311},"IC Programming","/pcba/ic-programming",{"label":313,"path":314},"Conformal Coating","/pcba/pcb-conformal-coating",{"label":316,"path":317},"Selective Soldering","/pcba/pcb-selective-soldering",{"label":319,"path":320},"BGA Reballing","/pcba/bga-reballing",{"label":322,"path":323},"Cable Assembly","/pcba/cable-assembly",{"label":325,"path":326},"Wire Harness","/pcba/harness-assembly",{"heading":328,"links":329},"Quality & Testing",[330,333,336,339,342,345,348,351,354,357],{"label":331,"path":332},"Quality Inspection","/pcba/quality-system",{"label":334,"path":335},"First Article Inspection (FAI)","/pcba/first-article-inspection",{"label":337,"path":338},"Solder Paste Inspection (SPI)","/pcba/spi-inspection",{"label":340,"path":341},"AOI Optical Inspection","/pcba/aoi-inspection",{"label":343,"path":344},"X-Ray / CT Inspection","/pcba/xray-inspection",{"label":346,"path":347},"ICT In-Circuit Testing","/pcba/ict-test",{"label":349,"path":350},"Flying Probe Testing","/pcba/flying-probe-testing",{"label":352,"path":353},"FCT / Functional Testing","/pcba/fct-test",{"label":355,"path":356},"Final Inspection & Packing","/pcba/final-quality-inspection",{"label":358,"path":359},"Incoming Quality Control","/pcba/incoming-quality-control",{"heading":361,"linkClass":362,"links":363},"Industry Applications (Entry)","text-nowrap",[364,367,370,373,376,379,382,385,388,391,394],{"label":365,"path":366},"Server / Data Center","/industries/server-data-center-pcb",{"label":368,"path":369},"Automotive / EV","/industries/automotive-electronics-pcb",{"label":371,"path":372},"Medical","/industries/medical-pcb",{"label":374,"path":375},"Telecom / 5G","/industries/communication-equipment-pcb",{"label":377,"path":378},"Aerospace & Defense","/industries/aerospace-defense-pcb",{"label":380,"path":381},"Drone / UAV","/industries/drone-uav-pcb",{"label":383,"path":384},"Industrial Control & Automation","/industries/industrial-control-pcb",{"label":386,"path":387},"Power & New Energy","/industries/power-energy-pcb",{"label":389,"path":390},"Robotics & Automation","/industries/robotics-pcb",{"label":392,"path":393},"Security / Security Equipment","/industries/security-equipment-pcb",{"label":395,"path":396},"PCB Industry Overview →","/pcb-industry-solutions",1780457701065]