[{"data":1,"prerenderedAt":397},["ShallowReactive",2],{"blog-aoi-spi-best-practices-en":3,"header-nav-en":69},{"title":4,"description":5,"date":6,"category":7,"image":8,"readingTime":9,"wordCount":10,"timeRequired":11,"htmlContent":12,"tags":13,"slug":19,"jsonld":20},"AOI and SPI Best Practices in PCBA: How to Split Ownership Without Overclaiming Coverage","A practical engineering guide to AOI and SPI best practices in PCBA, covering how each method fits in the build flow, what each one owns, and what still needs later inspection or release review.","2026-05-13","technology","/assets/img/blogs/2025/05/aoi-spi-best-practices.png",11,2154,"PT11M","\u003Cul>\n\u003Cli>AOI and SPI best practices start with a simple rule: \u003Cstrong>SPI owns solder-paste control before reflow, and AOI owns visible assembly review later in the flow\u003C/strong>.\u003C/li>\n\u003Cli>The safest inspection plan is not \u003Ccode>AOI or SPI\u003C/code>. It is \u003Cstrong>what defect class is being checked at what stage, and what evidence still has to come after that stage\u003C/strong>.\u003C/li>\n\u003Cli>A board can pass SPI and still fail AOI. A board can pass AOI and still require X-ray, ICT, flying probe, or functional test.\u003C/li>\n\u003Cli>SPI and AOI should be described as \u003Cstrong>separate layers in a larger PCBA quality stack\u003C/strong>, not as interchangeable proof tools.\u003C/li>\n\u003Cli>If a build includes hidden-joint packages, unstable first-build inputs, or release-critical electrical checks, AOI and SPI should be treated as upstream screening and process-control layers rather than complete shipment proof.\u003C/li>\n\u003C/ul>\n\u003Cblockquote>\n\u003Cp>\u003Cstrong>Quick Answer\u003C/strong>\nAOI and SPI best practices in PCBA come down to stage discipline and defect ownership. SPI should be used to control solder-paste deposition before placement and reflow. AOI should be used to review visible placement, polarity, geometry, and visible solder features later in the assembly flow. Neither method proves the whole board is ready to ship by itself, so a good plan keeps their boundaries clear and routes hidden-joint, electrical, and release questions to later gates.\u003C/p>\n\u003C/blockquote>\n\u003Cp>For the broader inspection-and-test stack that connects SPI, AOI, X-ray, ICT, flying probe, functional test, and final release review, start with the \u003Ca href=\"/en/blog/pcba-assembly-test-quality-guide\">PCBA Assembly Test and Quality Guide\u003C/a>.\u003C/p>\n\u003Ch2 id=\"table-of-contents\" data-anchor-en=\"table-of-contents\">Table of Contents\u003C/h2>\n\u003Cul>\n\u003Cli>\u003Ca href=\"#first-review\">What should engineers review first?\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"#what-spi-owns\">What does SPI actually own?\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"#what-aoi-owns\">What does AOI actually own?\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"#build-flow\">How should AOI and SPI be split in the build flow?\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"#when-they-matter\">When do AOI and SPI become more important?\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"#freeze-before-release\">What should be frozen before using AOI or SPI as release evidence?\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"#next-steps\">Next steps with APTPCB\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"#faq\">FAQ\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"#references\">Public references\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"#author\">Author and review information\u003C/a>\u003C/li>\n\u003C/ul>\n\u003Ca id=\"first-review\">\u003C/a>\n\u003Ch2 id=\"what-should-engineers-review-first\" data-anchor-en=\"what-should-engineers-review-first\">What should engineers review first?\u003C/h2>\n\u003Cp>Start with \u003Cstrong>inspection stage, defect class, visibility, and downstream dependency\u003C/strong>.\u003C/p>\n\u003Cp>That order matters because many weak \u003Ccode>AOI and SPI best practices\u003C/code> articles talk as if both methods answer the same question. They do not.\u003C/p>\n\u003Cp>The better planning question is:\u003C/p>\n\u003Cp>\u003Cstrong>Which defect class needs evidence first, and at what point in the assembly flow can that evidence still be trusted?\u003C/strong>\u003C/p>\n\u003Cp>The first review questions should be:\u003C/p>\n\u003Col>\n\u003Cli>Is the main concern solder-paste deposition before placement and reflow?\u003C/li>\n\u003Cli>Is the main concern visible placement, polarity, geometry, or visible solder features after assembly progresses?\u003C/li>\n\u003Cli>Are hidden joints or electrical faults still going to require later gates?\u003C/li>\n\u003Cli>Is this a first-build learning program or a more stable repeat build?\u003C/li>\n\u003C/ol>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Review axis\u003C/th>\n\u003Cth>What to check\u003C/th>\n\u003Cth>Why it matters\u003C/th>\n\u003Cth>What AOI or SPI alone does not prove\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>Inspection stage\u003C/td>\n\u003Ctd>Whether the issue sits before reflow or after assembled features are visible\u003C/td>\n\u003Ctd>Stage determines what can actually be inspected\u003C/td>\n\u003Ctd>Full shipment readiness\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Defect class\u003C/td>\n\u003Ctd>Whether the concern is paste-related or visible assembly-related\u003C/td>\n\u003Ctd>Keeps each method in its own lane\u003C/td>\n\u003Ctd>Hidden-joint or electrical coverage\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Visibility\u003C/td>\n\u003Ctd>Whether the risk is optically visible on the board surface\u003C/td>\n\u003Ctd>Optical methods only help where the defect can be seen\u003C/td>\n\u003Ctd>That concealed areas are defect-free\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Downstream dependency\u003C/td>\n\u003Ctd>Whether X-ray, ICT, flying probe, FCT, or final review still owns later proof\u003C/td>\n\u003Ctd>AOI and SPI are only part of the stack\u003C/td>\n\u003Ctd>End-to-end product validation\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Ca id=\"what-spi-owns\">\u003C/a>\n\u003Ch2 id=\"what-does-spi-actually-own\" data-anchor-en=\"what-does-spi-actually-own\">What does SPI actually own?\u003C/h2>\n\u003Cp>SPI owns \u003Cstrong>solder-paste deposition review before the rest of the SMT flow hides the printing result\u003C/strong>.\u003C/p>\n\u003Cp>That makes SPI an upstream process-control layer rather than a final assembled-board verdict.\u003C/p>\n\u003Cp>In practical terms, SPI is useful for checking whether the paste-printing stage appears to be under control before the board moves to placement and reflow. That is why SPI belongs early in the flow and why it is valuable even when later inspection layers still exist.\u003C/p>\n\u003Cp>What SPI is good for discussing safely:\u003C/p>\n\u003Cul>\n\u003Cli>solder-paste volume, height, area, or offset measurement\u003C/li>\n\u003Cli>missing paste or insufficient paste risk\u003C/li>\n\u003Cli>excess paste or bridging risk at the printing stage\u003C/li>\n\u003Cli>trend monitoring and upstream print-process feedback\u003C/li>\n\u003C/ul>\n\u003Cp>What SPI does not replace:\u003C/p>\n\u003Cul>\n\u003Cli>visible placement review after assembly progresses\u003C/li>\n\u003Cli>hidden-joint inspection under concealed packages\u003C/li>\n\u003Cli>assembled-board electrical fault screening\u003C/li>\n\u003Cli>powered functional behavior validation\u003C/li>\n\u003C/ul>\n\u003Cp>This is the key best-practice boundary:\u003C/p>\n\u003Cp>\u003Cstrong>Use SPI to stop upstream print defects early, but do not describe it as proof that the assembled board is already validated.\u003C/strong>\u003C/p>\n\u003Ca id=\"what-aoi-owns\">\u003C/a>\n\u003Ch2 id=\"what-does-aoi-actually-own\" data-anchor-en=\"what-does-aoi-actually-own\">What does AOI actually own?\u003C/h2>\n\u003Cp>AOI owns \u003Cstrong>visible assembly review\u003C/strong>.\u003C/p>\n\u003Cp>That usually includes:\u003C/p>\n\u003Cul>\n\u003Cli>component presence\u003C/li>\n\u003Cli>orientation and polarity\u003C/li>\n\u003Cli>placement shift or skew\u003C/li>\n\u003Cli>visible solder-feature anomalies\u003C/li>\n\u003Cli>some visible contamination or surface-level visual issues\u003C/li>\n\u003C/ul>\n\u003Cp>AOI is strongest when the defect can be reviewed as visible board-surface geometry or visible solder appearance.\u003C/p>\n\u003Cp>What AOI does not replace:\u003C/p>\n\u003Cul>\n\u003Cli>SPI for upstream solder-paste control\u003C/li>\n\u003Cli>X-ray for hidden joints and concealed solder regions\u003C/li>\n\u003Cli>ICT or flying probe for electrical fault coverage\u003C/li>\n\u003Cli>FCT for powered behavior\u003C/li>\n\u003C/ul>\n\u003Cp>That is why AOI should be framed as a visible-defect screening layer instead of a blanket \u003Ccode>quality passed\u003C/code> claim.\u003C/p>\n\u003Cp>Related reading:\u003C/p>\n\u003Cul>\n\u003Cli>\u003Ca href=\"/en/pcba/aoi-inspection\">AOI Inspection\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/pcba/spi-inspection\">SPI Inspection\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/pcba/xray-inspection\">X-Ray Inspection\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/pcba/testing-quality\">Testing & Quality\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/blog/aoi-inspection-pcba\">What AOI Inspection in PCBA Checks\u003C/a>\u003C/li>\n\u003C/ul>\n\u003Ca id=\"build-flow\">\u003C/a>\n\u003Ch2 id=\"how-should-aoi-and-spi-be-split-in-the-build-flow\" data-anchor-en=\"how-should-aoi-and-spi-be-split-in-the-build-flow\">How should AOI and SPI be split in the build flow?\u003C/h2>\n\u003Cp>The most useful split is stage-based.\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Method\u003C/th>\n\u003Cth>What it mainly answers\u003C/th>\n\u003Cth>Where it sits\u003C/th>\n\u003Cth>What it does not replace\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>SPI\u003C/td>\n\u003Ctd>Whether solder-paste deposition is under control before later assembly stages\u003C/td>\n\u003Ctd>Before placement and reflow\u003C/td>\n\u003Ctd>AOI, X-ray, or electrical test\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>AOI\u003C/td>\n\u003Ctd>Whether visible placement, polarity, geometry, and visible solder features look acceptable\u003C/td>\n\u003Ctd>Around placement or after reflow, depending on the inspection plan\u003C/td>\n\u003Ctd>SPI, hidden-joint inspection, or electrical test\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>That means \u003Ccode>AOI and SPI best practices\u003C/code> are really about disciplined sequencing:\u003C/p>\n\u003Cul>\n\u003Cli>SPI helps catch a printing problem before it becomes a later soldering or placement issue.\u003C/li>\n\u003Cli>AOI helps screen the visible assembled result once there is enough visible information to inspect.\u003C/li>\n\u003Cli>X-ray, ICT, flying probe, FCT, and final release review still answer other questions later.\u003C/li>\n\u003C/ul>\n\u003Cp>A common inspection-planning failure chain starts when SPI shows paste-volume drift, offset, or insufficient deposition on a fine-pitch or bottom-terminated package build, but the issue is treated as if AOI can cleanly own it later. Placement and reflow continue on a weak print baseline, the solder outcome shifts, and AOI then sees visible skew, bridging, polarity fallout, or insufficient-solder symptoms after the defect has already been amplified across more boards. The team is no longer stopping one upstream print excursion. It is spending reinspection, rework, and release-hold time on a downstream symptom because the stage owner was left vague.\u003C/p>\n\u003Cp>The most expensive version of that mistake shows up on BTC devices such as QFNs, power MOSFETs, and RF shield cans when teams skip 3D SPI to save cycle time and trust post-reflow AOI to catch what matters. If the stencil print leaves the central thermal pad short on volume or shifted off target, AOI cannot truly see the defect after reflow. The camera only sees the visible toe fillets around the edge, and those side features can still look clean enough to produce a confident \u003Ccode>PASS\u003C/code> result.\u003C/p>\n\u003Cp>That \u003Ccode>PASS\u003C/code> can be completely false. Under the package, the central pad may already contain massive voiding or a cold joint. Once those boards move into FCT or reach the customer, the hidden joint becomes a heat trap and the device can run into thermal runaway. At that point the issue is no longer an inspection escape you fix cheaply. It turns into destructive rework, scrap, or field failure on boards that were labeled good. This is the physical blind spot: AOI cannot rescue a missing SPI decision on solder-paste defects it was never able to see.\u003C/p>\n\u003Cp>The common planning errors are:\u003C/p>\n\u003Cul>\n\u003Cli>treating SPI and AOI as interchangeable because both are inspection tools\u003C/li>\n\u003Cli>treating AOI as if it makes X-ray unnecessary\u003C/li>\n\u003Cli>treating AOI or SPI as if either one proves shipment readiness by itself\u003C/li>\n\u003Cli>collapsing process control, visible inspection, and release governance into one generic \u003Ccode>quality passed\u003C/code> claim\u003C/li>\n\u003C/ul>\n\u003Ca id=\"when-they-matter\">\u003C/a>\n\u003Ch2 id=\"when-do-aoi-and-spi-become-more-important\" data-anchor-en=\"when-do-aoi-and-spi-become-more-important\">When do AOI and SPI become more important?\u003C/h2>\n\u003Cp>SPI matters more when \u003Cstrong>print quality is the early risk the team needs to control before placement and reflow hide it\u003C/strong>.\u003C/p>\n\u003Cp>That usually includes:\u003C/p>\n\u003Cul>\n\u003Cli>dense SMT builds\u003C/li>\n\u003Cli>fine-pitch or bottom-terminated package planning\u003C/li>\n\u003Cli>first-build learning where print stability is still being established\u003C/li>\n\u003Cli>assemblies where early paste-process control is a major predictor of later solder outcomes\u003C/li>\n\u003C/ul>\n\u003Cp>AOI matters more when \u003Cstrong>visible assembly correctness is the main concern\u003C/strong>.\u003C/p>\n\u003Cp>That often includes:\u003C/p>\n\u003Cul>\n\u003Cli>component presence and placement confirmation\u003C/li>\n\u003Cli>polarity review\u003C/li>\n\u003Cli>visible geometry issues\u003C/li>\n\u003Cli>visible solder-feature anomalies\u003C/li>\n\u003Cli>repeated visible-defect screening before later electrical or release gates\u003C/li>\n\u003C/ul>\n\u003Cp>At the same time, both methods become less complete when:\u003C/p>\n\u003Cul>\n\u003Cli>hidden-joint packages dominate the risk\u003C/li>\n\u003Cli>the board still lacks stable assembly inputs\u003C/li>\n\u003Cli>the most important release question is electrical or functional rather than optical\u003C/li>\n\u003C/ul>\n\u003Cp>The governing rule is:\u003C/p>\n\u003Cp>\u003Cstrong>Use SPI to own the paste stage, use AOI to own visible assembly, and do not ask either method to certify risks that belong to hidden-joint, electrical, or final release gates.\u003C/strong>\u003C/p>\n\u003Ca id=\"freeze-before-release\">\u003C/a>\n\u003Ch2 id=\"what-should-be-frozen-before-using-aoi-or-spi-as-release-evidence\" data-anchor-en=\"what-should-be-frozen-before-using-aoi-or-spi-as-release-evidence\">What should be frozen before using AOI or SPI as release evidence?\u003C/h2>\n\u003Cp>Before AOI or SPI results are used as real release evidence, freeze:\u003C/p>\n\u003Col>\n\u003Cli>the inspection stage being discussed\u003C/li>\n\u003Cli>the defect classes each inspection step is expected to own\u003C/li>\n\u003Cli>the visibility assumptions, especially where hidden joints matter\u003C/li>\n\u003Cli>the later plan for X-ray, electrical test, or functional validation where required\u003C/li>\n\u003Cli>the release boundary between process control, visible inspection, and final shipment review\u003C/li>\n\u003C/ol>\n\u003Cp>If those items are still moving, SPI and AOI can still provide useful engineering feedback, but their results should not be overstated as full product proof.\u003C/p>\n\u003Ca id=\"next-steps\">\u003C/a>\n\u003Ch2 id=\"next-steps-with-aptpcb\" data-anchor-en=\"next-steps-with-aptpcb\">Next steps with APTPCB\u003C/h2>\n\u003Cp>If your high-density PCBA is being dragged down by high rework rates, if you suspect the current supplier is hiding weak print quality behind AOI passes, or if you are worried that QFN or BGA defects are escaping into customer hands, the inspection plan is already too weak for production risk.\u003C/p>\n\u003Cp>Send the Gerber or ODB++, BOM, stencil intent, and any defect logs or NCMRs to \u003Ca href=\"mailto:sales@aptpcb.com\">sales@aptpcb.com\u003C/a>, or route the build through the \u003Ca href=\"/en/quote\">quote page\u003C/a>.\u003C/p>\n\u003Cp>APTPCB's SMT process and quality engineering team will return an \u003Cstrong>Inspection Coverage & Quality Gate Review\u003C/strong> within 24 hours. The review will define realistic SPI volumetric limits, mark the physical blind spots between AOI and X-ray, and lock a quality-gate strategy designed to eliminate false accepts before you commit to expensive volume output.\u003C/p>\n\u003Cp>If you need to review the surrounding support pages first, use:\u003C/p>\n\u003Cul>\n\u003Cli>\u003Ca href=\"/en/blog/pcba-assembly-test-quality-guide\">PCBA Assembly Test and Quality Guide\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/pcba/spi-inspection\">SPI Inspection\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/pcba/aoi-inspection\">AOI Inspection\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/pcba/testing-quality\">Testing & Quality\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/pcba/final-quality-inspection\">Final Quality Inspection\u003C/a>\u003C/li>\n\u003C/ul>\n\u003Cdiv data-component=\"BlogQuickQuoteInline\">\u003C/div>\n\n\u003Ca id=\"faq\">\u003C/a>\n\u003Ch2 id=\"faq\" data-anchor-en=\"faq\">FAQ\u003C/h2>\n\u003C!-- faq:start -->\n\n\u003Ch3 id=\"is-spi-the-same-as-aoi\" data-anchor-en=\"is-spi-the-same-as-aoi\">Is SPI the same as AOI?\u003C/h3>\n\u003Cp>No. SPI checks solder-paste deposition before later SMT stages. AOI checks visible assembly features later in the flow.\u003C/p>\n\u003Ch3 id=\"if-a-board-passes-spi-can-it-still-fail-aoi\" data-anchor-en=\"if-a-board-passes-spi-can-it-still-fail-aoi\">If a board passes SPI, can it still fail AOI?\u003C/h3>\n\u003Cp>Yes. A board can pass the paste stage and still develop visible placement or visible solder-feature issues later.\u003C/p>\n\u003Ch3 id=\"if-a-board-passes-aoi-do-i-still-need-x-ray\" data-anchor-en=\"if-a-board-passes-aoi-do-i-still-need-x-ray\">If a board passes AOI, do I still need X-ray?\u003C/h3>\n\u003Cp>Sometimes yes. AOI does not replace hidden-joint inspection when concealed solder areas need evidence.\u003C/p>\n\u003Ch3 id=\"can-aoi-replace-ict-or-flying-probe\" data-anchor-en=\"can-aoi-replace-ict-or-flying-probe\">Can AOI replace ICT or flying probe?\u003C/h3>\n\u003Cp>No. AOI is an optical method. ICT and flying probe are electrical-verification methods for different defect classes.\u003C/p>\n\u003Ch3 id=\"what-is-the-biggest-mistake-in-aoi-and-spi-planning\" data-anchor-en=\"what-is-the-biggest-mistake-in-aoi-and-spi-planning\">What is the biggest mistake in AOI and SPI planning?\u003C/h3>\n\u003Cp>Treating both methods as interchangeable inspection names instead of keeping the stage boundary and defect ownership clear.\u003C/p>\n\u003C!-- faq:end -->\n\n\u003Ca id=\"references\">\u003C/a>\n\u003Ch2 id=\"public-references\" data-anchor-en=\"public-references\">Public references\u003C/h2>\n\u003Col>\n\u003Cli>\u003Cp>\u003Ca href=\"/en/pcba/spi-inspection\">APTPCB SPI Inspection\u003C/a>\nSupports SPI as the upstream solder-paste inspection layer before later assembly stages.\u003C/p>\n\u003C/li>\n\u003Cli>\u003Cp>\u003Ca href=\"/en/pcba/aoi-inspection\">APTPCB AOI Inspection\u003C/a>\nSupports AOI as the visible assembly inspection layer.\u003C/p>\n\u003C/li>\n\u003Cli>\u003Cp>\u003Ca href=\"/en/pcba/testing-quality\">APTPCB Testing & Quality\u003C/a>\nSupports the broader layered relationship between inspection, electrical verification, and release governance.\u003C/p>\n\u003C/li>\n\u003Cli>\u003Cp>\u003Ca href=\"/en/pcba/final-quality-inspection\">APTPCB Final Quality Inspection\u003C/a>\nSupports final review as a later release gate rather than an SPI or AOI substitute.\u003C/p>\n\u003C/li>\n\u003Cli>\u003Cp>\u003Ca href=\"https://kohyoung.com/en/solder-paste-inspection-technology\">Koh Young: Solder Paste Inspection Technology\u003C/a>\nSupports SPI as an upstream solder-paste measurement and process-control method.\u003C/p>\n\u003C/li>\n\u003Cli>\u003Cp>\u003Ca href=\"https://kohyoung.com/en/automated-optical-inspection-technology\">Koh Young: Automated Optical Inspection Technology\u003C/a>\nSupports AOI as an optical inspection method for visible assembly defects and solder features.\u003C/p>\n\u003C/li>\n\u003Cli>\u003Cp>\u003Ca href=\"https://www.keysight.com/us/en/products/in-circuit-test-for-manufacturing/in-circuit-test-systems.html\">Keysight: In-Circuit Test Systems\u003C/a>\nSupports ICT as a separate electrical-verification layer rather than an optical-inspection function.\u003C/p>\n\u003C/li>\n\u003C/ol>\n\u003Ca id=\"author\">\u003C/a>\n\u003Ch2 id=\"author-and-review-information\" data-anchor-en=\"author-and-review-information\">Author and review information\u003C/h2>\n\u003Cul>\n\u003Cli>Author: APTPCB PCBA inspection content team\u003C/li>\n\u003Cli>Technical review: SMT process control and inspection engineering team\u003C/li>\n\u003Cli>Last updated: 2026-05-15\u003C/li>\n\u003C/ul>\n\n\u003Csection class=\"related-links\" aria-label=\"Related\">\u003Ch3>Related links\u003C/h3>\u003Cul>\u003Cli>\u003Ca href=\"/en/blog/pcba-assembly-test-quality-guide\">PCBA Assembly Test and Quality Guide\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/pcba/aoi-inspection\">AOI Inspection\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/pcba/spi-inspection\">SPI Inspection\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/pcba/xray-inspection\">X-Ray Inspection\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/pcba/testing-quality\">Testing & Quality\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/aoi-inspection-pcba\">What AOI Inspection in PCBA Checks\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/quote\">quote page\u003C/a>\u003C/li>\u003C/ul>\u003C/section>",[14,15,16,17,18],"aoi spi best practices","spi vs aoi","pcba inspection","aoi inspection","spi inspection","aoi-spi-best-practices",{"blog":21,"breadcrumb":30,"faq":44},{"@context":22,"@type":23,"headline":4,"description":5,"image":8,"url":24,"datePublished":6,"dateModified":6,"timeRequired":11,"keywords":25,"articleSection":7,"author":26,"publisher":29},"https://schema.org","BlogPosting","https://aptpcb.com/en/blog/aoi-spi-best-practices","aoi spi best practices, spi vs aoi, pcba inspection, aoi inspection, spi inspection",{"@type":27,"name":28},"Organization","APTPCB",{"@type":27,"name":28},{"@context":22,"@type":31,"itemListElement":32},"BreadcrumbList",[33,38,42],{"@type":34,"position":35,"name":36,"item":37},"ListItem",1,"Home","https://aptpcb.com/",{"@type":34,"position":39,"name":40,"item":41},2,"Blog","https://aptpcb.com/en/blog",{"@type":34,"position":43,"name":19,"item":24},3,{"@context":22,"@type":45,"mainEntity":46},"FAQPage",[47,53,57,61,65],{"@type":48,"name":49,"acceptedAnswer":50},"Question","Is SPI the same as AOI?",{"@type":51,"text":52},"Answer","No. SPI checks solder-paste deposition before later SMT stages. AOI checks visible assembly features later in the flow.",{"@type":48,"name":54,"acceptedAnswer":55},"If a board passes SPI, can it still fail AOI?",{"@type":51,"text":56},"Yes. A board can pass the paste stage and still develop visible placement or visible solder-feature issues later.",{"@type":48,"name":58,"acceptedAnswer":59},"If a board passes AOI, do I still need X-ray?",{"@type":51,"text":60},"Sometimes yes. AOI does not replace hidden-joint inspection when concealed solder areas need evidence.",{"@type":48,"name":62,"acceptedAnswer":63},"Can AOI replace ICT or flying probe?",{"@type":51,"text":64},"No. AOI is an optical method. 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